yetangitu/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2025-10-03 09:49:23 +02:00
Code Issues Releases Wiki Activity

tmp assigned rd0 instead of LR

Browse source
This commit is contained in:
srichmo1 2023-09-05 10:03:20 -04:00 • committed by ghidorahrex
parent be7458a436
commit 24b2275c0b
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
Ghidra/Processors/Atmel/data/languages/avr32a_instruction_flow.sinc
View file

@ -154,7 +154,7 @@ RJMPdisp: disp is disp4_8 & sdisp0_2
# 0101 1101 0001 dddd # 0101 1101 0001 dddd
:ICALL rd0 is op4_12=0x5d1 & rd0 { :ICALL rd0 is op4_12=0x5d1 & rd0 {
tmp:4 = LR; tmp:4 = rd0;
LR = inst_next; LR = inst_next;
call [tmp]; call [tmp];
} }