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ARM: Handle disassembly of conditional VNMUL for F32/F64

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The single-precision and double-precision variants of VNMUL support
condition codes on them in ARM mode. We can amend the Sleigh
constructors to reflect this.

We can also amend the half-precision variant to reflect that the
condition code should be 0xE in terms of value. The ARMv8 architecture
reference manual states (at F6.1.148) that if a half-precision
instruction is present and does not have a condition code of 1110, then
the behavior is considered CONSTRAINED UNPREDICTABLE.

This fixes VNMUL instructions disassembling as generic CDP instructions,
making the disassembly much clearer.
This commit is contained in:
Lioncash 2019-11-24 01:29:15 -05:00
parent 844915e935
commit 9670b81458
1 changed files with 13 additions and 13 deletions
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6
Ghidra/Processors/ARM/data/languages/ARMneon.sinc
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@ -3173,21 +3173,21 @@ define pcodeop FloatVectorNeg;
Sd = zext(product);
}
:vnmul.f64 Dd,Dn,Dm is COND & ( ($(AMODE) & cond=15 & c2327=0x1c & c2021=2 & c0811=11 & c0606=1 & c0404=0) |
:vnmul^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & COND & c2327=0x1c & c2021=2 & c0811=11 & c0606=1 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0) ) & Dm & Dn & Dd
{
product:8 = Dn f* Dm;
Dd = 0 f- product;
}
:vnmul.f32 Sd,Sn,Sm is COND & ( ($(AMODE) & cond=15 & c2327=0x1c & c2021=2 & c0811=10 & c0606=1 & c0404=0) |
:vnmul^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & COND & c2327=0x1c & c2021=2 & c0811=10 & c0606=1 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sn & Sd
{
product:4 = Sn f* Sm;
Sd = 0 f- product;
}
:vnmul.f16 Sd,Sn,Sm is COND & ( ($(AMODE) & cond=15 & c2327=0x1c & c2021=2 & c0811=9 & c0606=1 & c0404=0) |
:vnmul.f16 Sd,Sn,Sm is ( ($(AMODE) & cond=0xe & c2327=0x1c & c2021=2 & c0811=9 & c0606=1 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=9 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sn & Sd
{
product:2 = Sn:2 f* Sm:2;