mirror of
https://github.com/NationalSecurityAgency/ghidra.git
synced 2025-10-03 17:59:46 +02:00
Opinion fix
Does not handle all the cases it can, add in size IMAFC and generic cases for GC.
This commit is contained in:
parent
c9ae8bdd8d
commit
a487f77918
1 changed files with 12 additions and 9 deletions
|
@ -11,15 +11,18 @@
|
|||
<!-- EF_RISCV_ABI_QUAD 0x0006 -->
|
||||
<!-- EF_RISCV_RVE 0x0008 -->
|
||||
<!-- EF_RISCV_TSO 0x0010 -->
|
||||
<constraint primary="243" secondary="0" processor="RISCV" endian="little" variant="RV32I"/>
|
||||
<constraint primary="243" secondary="0" processor="RISCV" endian="little" variant="RV64I"/>
|
||||
<constraint primary="243" secondary="1" processor="RISCV" endian="little" variant="RV32IMC"/>
|
||||
<constraint primary="243" secondary="1" processor="RISCV" endian="little" variant="RV64IC"/>
|
||||
<constraint primary="243" secondary="2" processor="RISCV" endian="little" variant="RV32IF"/>
|
||||
<constraint primary="243" secondary="4" processor="RISCV" endian="little" variant="RV32G"/>
|
||||
<constraint primary="243" secondary="4" processor="RISCV" endian="little" variant="RV64G"/>
|
||||
<constraint primary="243" secondary="5" processor="RISCV" endian="little" variant="RV32GC"/>
|
||||
<constraint primary="243" secondary="5" processor="RISCV" endian="little" variant="RV64GC"/>
|
||||
<constraint primary="243" secondary="0" processor="RISCV" endian="little" size="32" variant="RV32I"/>
|
||||
<constraint primary="243" secondary="0" processor="RISCV" endian="little" size="64" variant="RV64I"/>
|
||||
<constraint primary="243" secondary="1" processor="RISCV" endian="little" size="32" variant="RV32IMC"/>
|
||||
<constraint primary="243" secondary="1" processor="RISCV" endian="little" size="64" variant="RV64IC"/>
|
||||
<constraint primary="243" secondary="2" processor="RISCV" endian="little" size="32" variant="RV32IF"/>
|
||||
<constraint primary="243" secondary="3" processor="RISCV" endian="little" size="32" variant="RV32GC"/> <!-- RV32IMAFC -->
|
||||
<constraint primary="243" secondary="4" processor="RISCV" endian="little" size="32" variant="RV32G"/>
|
||||
<constraint primary="243" secondary="4" processor="RISCV" endian="little" size="64" variant="RV64G"/>
|
||||
<constraint primary="243" secondary="5" processor="RISCV" endian="little" size="32" variant="RV32GC"/>
|
||||
<constraint primary="243" secondary="5" processor="RISCV" endian="little" size="64" variant="RV64GC"/>
|
||||
<constraint primary="243" processor="RISCV" endian="little" size="32" variant="RV32GC"/>
|
||||
<constraint primary="243" processor="RISCV" endian="little" size="64" variant="RV64GC"/>
|
||||
</constraint>
|
||||
</constraint>
|
||||
</opinions>
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue