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'origin/GP-4254_ghidorahrex_PR-6113_marcushall42_xtensa_bany_fix'
(Closes #6113)
This commit is contained in:
Ryan Kurtz 2024-02-08 13:17:22 -05:00
commit a9ef8804ef
2 changed files with 10 additions and 4 deletions
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4
Ghidra/Processors/Xtensa/data/languages/xtensa.ldefs
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@ -5,7 +5,7 @@
endian="little" endian="little"
size="32" size="32"
variant="default" variant="default"
version="4.0" version="4.1"
slafile="xtensa_le.sla" slafile="xtensa_le.sla"
processorspec="xtensa.pspec" processorspec="xtensa.pspec"
manualindexfile="../manuals/xtensa.idx" manualindexfile="../manuals/xtensa.idx"
@ -19,7 +19,7 @@
endian="big" endian="big"
size="32" size="32"
variant="default" variant="default"
version="4.0" version="4.1"
slafile="xtensa_be.sla" slafile="xtensa_be.sla"
processorspec="xtensa.pspec" processorspec="xtensa.pspec"
manualindexfile="../manuals/xtensa.idx" manualindexfile="../manuals/xtensa.idx"

10
Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc
View file

@ -122,7 +122,7 @@
# BANY - Branch if Any Bit Set, pg. 265. # BANY - Branch if Any Bit Set, pg. 265.
:bany srel_16_23, as, at, is srel_16_23 & ar = 0b1000 & as & at & op0 = 0b0111 { :bany srel_16_23, as, at, is srel_16_23 & ar = 0b1000 & as & at & op0 = 0b0111 {
local test:4 = as & at; local test:4 = as & at;
if (test == 0) goto srel_16_23; if (test != 0) goto srel_16_23;
} }
macro extract_bit(bit, result) { macro extract_bit(bit, result) {
@ -399,7 +399,7 @@ macro extract_bit(bit, result) {
local mt:1 = (x s> (-clamp)); local mt:1 = (x s> (-clamp));
local max:4 = (zext(mt) * x) + (zext(!mt) * (-clamp)); local max:4 = (zext(mt) * x) + (zext(!mt) * (-clamp));
mt = (x s< (clamp-1)); mt = (x s< (clamp-1));
local y = (zext(mt) * max) + (zext(!mt) * (clamp-1)); ar = (zext(mt) * max) + (zext(!mt) * (clamp-1));
} }
# DHI - Data Cache Hit Invalidate, pg. 313. # DHI - Data Cache Hit Invalidate, pg. 313.
@ -1166,6 +1166,12 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist
local tmp:4 = as << shift; local tmp:4 = as << shift;
ar = tmp s>> shift; ar = tmp s>> shift;
} }
:sext ar, as, 7 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u4_4_7 = 0 & op0 = 0 {
ar = sext(as:1);
}
:sext ar, as, 15 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u4_4_7 = 8 & op0 = 0 {
ar = sext(as:2);
}
# SICT - Store Instruction Cache Tag, pg. 519. # SICT - Store Instruction Cache Tag, pg. 519.
:sict at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b0001 & as & at & op0 = 0 { :sict at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b0001 & as & at & op0 = 0 {