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fix vfnma 32 bits and make all part of vfpv4

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This commit is contained in:
Antonio Flores Montoya 2021-07-15 14:15:03 -04:00
parent 9230473b22
commit f555d0dcb7
5 changed files with 14 additions and 10 deletions
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1
Ghidra/Processors/ARM/data/languages/ARM7_be.slaspec
View file

@ -10,6 +10,7 @@
@define VERSION_7M ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"

1
Ghidra/Processors/ARM/data/languages/ARM7_le.slaspec
View file

@ -10,6 +10,7 @@
@define VERSION_7M ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"

1
Ghidra/Processors/ARM/data/languages/ARM8_be.slaspec
View file

@ -11,6 +11,7 @@
@define VERSION_8 ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"

1
Ghidra/Processors/ARM/data/languages/ARM8_le.slaspec
View file

@ -11,6 +11,7 @@
@define VERSION_8 ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"

20
Ghidra/Processors/ARM/data/languages/ARMneon.sinc
View file

@ -1818,7 +1818,7 @@ extImm: "#"^thv_c0811 is TMode=1 & thv_c0811 { tmp:1 = thv_c0811; export tmp; }
# VFMA VFMS VFNMA and VFNMS
#
@if defined(VFPv2) || defined(VFPv3)
@if defined(VFPv4)
:vfma^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c0811=10 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd
@ -1844,31 +1844,31 @@ extImm: "#"^thv_c0811 is TMode=1 & thv_c0811 { tmp:1 = thv_c0811; export tmp; }
Dd = Dd f- (Dn f* Dm);
}
:vfnma^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=10 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=1 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd
:vfnma^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=10 & c0606=1 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = Sd f+ ((0 f- Sn) f* Sm);
}
:vfnma^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=11 & c0606=0 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0)) & Dm & Dn & Dd
:vfnma^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=11 & c0606=1 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0)) & Dm & Dn & Dd
{
Dd = Dd f+ ((0 f- Dn) f* Dm);
}
:vfnms^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=10 & c0606=1 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=1 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd
:vfnms^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=10 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = Sd f- ((0 f- Sn) f* Sm);
}
:vfnms^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=11 & c0606=1 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0)) & Dm & Dn & Dd
:vfnms^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=11 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0)) & Dm & Dn & Dd
{
Dd = Dd f- ((0 f- Dn) f* Dm);
}
@endif # VFPv2 || VFPv3
@endif # VFPv4
#######
# VLD1 (multiple single elements)