Create macros for push/pop instructions, which operates of segment registers. Add behaviour for
push/pop instructions, which operates of `FS` and `GS` segment registers in 64-bit mode.
For details see p. 1037 (`POP`) and p. 1163 (`PUSH`) of Intel's manual or open `Instruction Info...`
in the Ghidra.
Fix#1377.
shortcut to address space map
more adjustments to shortcuts
allow null AddrSpace pointer in raw baselist
holes in the space indices
almost working
GT-2873 decompiler, other, and overlays
GT-2873 added OTHER space to java sleigh compiler, fixed decompiler
exception
isOtherSpace method
isOtherSpace java, addressing code review comments
GT-2873 added null check in decompiler reset
GT-2873 code review changes
Read and write space_other tag in SLA files
Version number for .sla file
GT-2873 fixups after merge
GT-2873 renamed Sparc registers: OTHER->OTHERWIN, WINWSTATE->WSTATE
GT-2873 added option in AddressInput to control OTHER space visibility
GT-2873 OTHER space now global
GT-2873 fixing comments refering to decompiler code in BasicCompilerSpec
The SAHF/LAHF instructions date from the 32bit x86 days, and where initially
marked as obsolete in the AMD 64bit spec. All processors have the requisite
logic, as they are backwards compatible in 32bit mode.
The original 64bit CPUs from Intel and AMD would raise #UD for these
instructions, per the AMD64 spec.
However, they were were sufficiently critical for software emulators that the
instructions were "reintroduced" into the AMD64 spec, with a new CPUID bit
indicating that the they were now usable in 64bit mode.
In practice, every 64bit capable processor since 2005 has supported them.
Fixes#837
Several x86_64 instructions were not sign extending the imm32 to
64-bits for the 64-bit mode instruction: ADD, AND, CMD, and SUB,
while: ADC, MOV, and TEST were correct
* `CC` and `CD 03` are different instructions, but previously disassembled to
`INT 3` and `INT 0x3` respectively.
The proper mnemonic for the former is `INT3` (no space), while the latter
is a byte sequence only seen in tests and when trying to exploit emulator
bugs. Switch `CC` to use its documented mnemonic, which makes it easier to
distinguish.
* `INT1`, also commonly known as `ICEBP` (In Circuit Emulator Break-Point)
has existed since the 486 processor, and was finally documented by Intel
following the fallout from CVE-2018-8897. Model it after `INT3`.
* It is unclear why there is a specialisation for `:INT n29`, because vector
29 is `#VC` in newer AMD CPUs, and can't be invoked using the `INT $29`
instruction anyway.
The byte sequence `CC 1D` always gets disassembled using `:INT imm8`, which
suggests that SLEIGH has noticed the redundancy and folded the decode
rules. Drop the specialisation.
Fixes#514
