mumbel
6f3fc3c32e
x86 consistent offsets
2019-07-24 19:51:04 -05:00
Ryan Kurtz
674d5cee53
Merge remote-tracking branch 'origin/GT-3015_ryanmkurtz_PR-756_Piruzzolo_AAM'
2019-07-18 08:48:30 -04:00
ghidra1
e565601299
Merge remote-tracking branch 'origin/ghidra1_BitFields'
2019-07-17 18:45:27 -04:00
Ryan Kurtz
a4f7cdc414
Merge remote-tracking branch 'origin/GT-2940_GhidorahRex_PR_Support_for_RD_WR_FS_GS_BASE'
2019-07-17 12:33:49 -04:00
ghidra1
a7345527c9
BitFields - added preliminary support for composite bitfields
2019-07-17 11:55:29 -04:00
Ryan Kurtz
7a696dd6c2
Merge remote-tracking branch 'origin/GT-3007_ryanmkurtz_PR-719_williballenthin_patterncontraints'
2019-07-17 09:21:43 -04:00
Ryan Kurtz
c6f0bbc614
Merge remote-tracking branch 'origin/GT-3006_ryanmkurtz_PR-671_marpie_implement_callfixup_chkstk'
2019-07-17 09:01:23 -04:00
Ryan Kurtz
a4b9304cd8
Merge remote-tracking branch 'origin/GT-3004_ryanmkurtz_PR-771_GregoryMorse_x86_16_ida'
2019-07-17 08:19:50 -04:00
caheckman
12d3da029b
Refactor ParamEntry look-up allowing "contained by" discovery
2019-07-15 15:15:37 -04:00
caheckman
ef12c20829
Fix for "Unknown function tag: scope" error
2019-07-15 15:13:11 -04:00
Gregory Morse
70a7d03099
Update x86.ldefs
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x86 16-bit in IDA Pro >= 7.0 and probably earlier uses the metapc processor type and not any of those listed anymore. I am not sure how many others should also be included but probably all of them. The bit size is the primary selection, not the processor type anymore so although metapc is confirmed, perhaps the following should also be added as they are under 32-bit:
<external_name tool="IDA-PRO" name="80686p"/>
<external_name tool="IDA-PRO" name="k62"/>
<external_name tool="IDA-PRO" name="p2"/>
<external_name tool="IDA-PRO" name="p3"/>
<external_name tool="IDA-PRO" name="athlon"/>
<external_name tool="IDA-PRO" name="p4"/>
Though this is certainly a legacy IDA 5.x and maybe 6.x issue mainly. AFAIK, all the >= 7.0 IDA versions use metapc for all x86. Specific processors were any early feature that was consolidated there.
2019-07-10 01:57:16 +02:00
Piruzzolo
b549c0d8fc
removes unneeded == 1
2019-07-09 17:42:29 +02:00
Piruzzolo
d98290061d
Fix AAA, AAM, DAA, DAS x86 intructions + typo fix
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According to Intel manual, the AAM instruction has a MOD, not an AND. Likely a typo. More, (AF == 1) added instead of AF (but I think it's pretty much the same)
+ bonus typo fix
2019-07-04 01:02:55 +02:00
Willi Ballenthin
b0f6af4930
x86/data/patterns/patternconstraints: remove extra text node
...
removing a line that appears to be superfluous. also, fix indentation.
unfortunately, i have *not* tested this, as i noticed this apparent extra line during a visual inspection. i don't have a build environment currently configured.
2019-06-24 15:04:37 -06:00
Ryan Kurtz
a1d68852ca
Merge remote-tracking branch 'origin/GT-2943_GhidorahRex_PR-kreeblah_Update_x86_manual_index'
2019-06-20 07:59:03 -04:00
Markus Piéton
dce4f0a074
Implement Callfixup for x64 __chkstk function.
2019-06-10 17:02:41 +02:00
Andrew Cooper
28d473fed9
x86: Support for {RD,WR}{FS,GS}BASE instructions
...
This was derived from the existing readPID instruction, whose encoding is very
similar.
Fixes #554
2019-05-06 19:35:08 +01:00
Markus Piéton
bdcbe2cf3a
Callfixup for _guard_dispatch_icall on x86-64-win
...
Change goto to call
As pointed out by @caheckman [here](https://github.com/NationalSecurityAgency/ghidra/pull/340#issuecomment-482248465 ) the `goto` should be a `call`.
2019-04-15 11:15:12 -04:00
Kreeblah
b00852877c
Updated x86 manual index
...
Updated x86 manual indexes to the following:
Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2 (2A, 2B, 2C & 2D): Instruction Set Reference, A-Z, Sep 2016 (325383-060US), available at https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Rev 3.26 May 2018 (24594), available at https://www.amd.com/system/files/TechDocs/24594.pdf
AMD64 Architecture Programmer's Manual Volume 4: 128-Bit and 256-Bit Media Instructions, Rev 3.23 Feb 2019 (26568), available at https://www.amd.com/system/files/TechDocs/26568.pdf
AMD64 Architecture Programmer's Manual Volume 5: 64-Bit Media and x87 Floating-Point Instructions, Rev 3.15 May 2018 (26569), available at https://www.amd.com/system/files/TechDocs/26569_APM_v5.pdf
AMD64 Technology 128-Bit SSE5 Instruction Set, Rev 3.01 August 2007 (43479), which is unchanged from the provided .idx. I can't find a newer version of the publication (or a different publication) that lists the same instructions, so I left it as it was. The only copy of the actual publication that I can find is at http://www.cs.northwestern.edu/~pdinda/icsclass/doc/AMD_ARCH_MANUALS/AMD64_128_Bit_SSE5_Instrs.pdf but it looks to be incomplete, as it stops at ROUNDSS.
2019-04-06 09:56:12 -07:00
ghidra1
7179c6de81
GT-2667 added support for generating sleigh build.xml files
2019-03-29 17:24:31 -04:00
Dan
79d8f164f8
Candidate release of source code.
2019-03-26 13:46:51 -04:00
