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14607 commits 3 branches 48 tags 436 MiB
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1680 commits

Author SHA1 Message Date
Ryan Kurtz
8f3f5c18f5 Merge remote-tracking branch 'origin/GT-3008_ghidorahrex_PIC-30_division_instructions' 2019-08-09 13:50:31 -04:00
paramjot@gmail.com
276ee657aa super-h: Corrected bsrf and jsr instructions 2019-08-08 21:59:58 -04:00
ghidorahrex
a22c168878 Moved M8C for release. 2019-08-08 12:52:43 -04:00
ghidorahrex
864235ee7d Moved SuperH4 processor for release. 2019-08-08 12:11:45 -04:00
fortenbt
c992585957 Remove IO default memory block from 6502 pspec 
- Corrects the length of the zero page and stack memory blocks.
 2019-08-07 12:03:36 -04:00
mumbel
88f127566c Sign-extended imm32 for 64-bit mode 
Several x86_64 instructions were not sign extending the imm32 to
64-bits for the 64-bit mode instruction:  ADD, AND, CMD, and SUB,
while: ADC, MOV, and TEST were correct
 2019-08-06 17:40:53 -05:00
ghidorahrex
6a75b66995 PIC 30 code review fixes. Changed "repeat 0x12" to "repeat 0x11". 
Modified plain division instructions to use pcodeops since we can't
implement the normal instructions.
 2019-08-06 12:02:13 -04:00
paramjot@gmail.com
bab4788add Added #ifdef around shad/shld so the instructions are SH-2A only. 2019-08-04 23:44:52 -04:00
Andrew Cooper
97b4528388 x86: Improvements to breakpoint disassembly 
* `CC` and `CD 03` are different instructions, but previously disassembled to
   `INT 3` and `INT 0x3` respectively.

   The proper mnemonic for the former is `INT3` (no space), while the latter
   is a byte sequence only seen in tests and when trying to exploit emulator
   bugs.  Switch `CC` to use its documented mnemonic, which makes it easier to
   distinguish.

 * `INT1`, also commonly known as `ICEBP` (In Circuit Emulator Break-Point)
   has existed since the 486 processor, and was finally documented by Intel
   following the fallout from CVE-2018-8897.  Model it after `INT3`.

 * It is unclear why there is a specialisation for `:INT n29`, because vector
   29 is `#VC` in newer AMD CPUs, and can't be invoked using the `INT $29`
   instruction anyway.

   The byte sequence `CC 1D` always gets disassembled using `:INT imm8`, which
   suggests that SLEIGH has noticed the redundancy and folded the decode
   rules.  Drop the specialisation.

Fixes #514
 2019-08-03 19:13:53 +01:00
mumbel
63031e6fdd Cleanup SHAD and SHLD 2019-08-02 16:05:38 -05:00
Ryan Kurtz
15ee804009 Merge remote-tracking branch 'origin/GT-3058_emteere_PR-638_zeldin_8048' 2019-08-02 15:29:45 -04:00
emteere
3d9525985b GT-3058: Constrained matching so that order of instruction definitions 
don't matter.

Pulled-from: Marcus Comstedt <marcus@mc.pp.se>
 2019-08-02 15:19:40 -04:00
emteere
2221510f90 emteere Minor changes for sleigh editor syntax errors 2019-08-02 12:04:47 -04:00
Ryan Kurtz
64e83b1d93 Merge remote-tracking branch 'origin/GT-3041_emteere_PR-567_mumbel_tricore' 2019-08-02 11:34:38 -04:00
emteere
0a517e6864 GT-3041_emteere Added emulation tests and minor changes to calling 
convention.  Assigning correct return storage will require a separate
change to core Ghidra.

Pulled-from: mumbel <22204578+mumbel@users.noreply.github.com>
 2019-08-02 10:45:33 -04:00
paramjot@gmail.com
1601eee21a split mov.(b,l,w) instructions into two as requested in code review 2019-07-31 00:02:40 -04:00
mumbel
b1833266e0 fixup a refactor bug in shifting 2019-07-30 17:30:32 -05:00
mumbel
e6b6004b79 minor 2a cleanup 2019-07-30 17:25:23 -05:00
mumbel
922fa5c555 constructor for PC based mov 2019-07-30 17:17:18 -05:00
ghidorahrex
071f98e18b Added support for operand-size override (0x66) prefix on :movbe 
instructions.
 2019-07-30 08:30:37 -04:00
Guy Zana
5974048c99 super-h: fixed code review comments - 2 2019-07-30 08:45:53 +03:00
Guy Zana
63a8d9f216 super-h: fixed code review comments by @mumbel 2019-07-30 08:45:53 +03:00
Guy Zana
11833459e5 super-h: Added SuperH-2A and FPU support 2019-07-30 08:45:53 +03:00
Guy Zana
20edb02cf7 super-h: minor fixes and cleanups 2019-07-30 08:44:38 +03:00
paramjot@gmail.com
0d4d1eb7bd Removed extra whitespace in mov operand 2019-07-30 00:04:57 -04:00
paramjot@gmail.com
5f1e353e1c Implemented code review changes 2019-07-29 23:29:38 -04:00
Gareth Edwards
4da786f3f9 6805 definition - fix vendor in sla spec comment 
The 6805 is/was a Motorola architecture, not an Intel one. Fix the comment in the
slaspec file.
 2019-07-26 22:17:34 +01:00
mumbel
6f3fc3c32e x86 consistent offsets 2019-07-24 19:51:04 -05:00
Ryan Kurtz
f33e2c1296 Merge remote-tracking branch 
'origin/GT-3028_ghidorahrex_PR_marpie_Update_MIPS_processor_manuals'

Conflicts:
	Ghidra/Processors/MIPS/data/manuals/mipsMic.idx
 2019-07-23 09:03:50 -04:00
Ryan Kurtz
bb8f35f94d Merge remote-tracking branch 'origin/GT-3027_ghidorahrex_PR_philpem_ARM_TEQP_instruction' 2019-07-23 08:28:55 -04:00
ghidra1
5cde1bd48d GT-3026 - added support for ELF MIPS R_MIPS_GPREL32 relocation and 
corrected local R_MIPS_GPREL16 relocation.
 2019-07-22 17:52:36 -04:00
mumbel
56d427ce50 [tricore] Update gradle for 9.1.x changes 2019-07-19 18:46:11 -05:00
Marcus Comstedt
62d5fa3b9d 8048: Remove the localrange declaration for the stack 2019-07-19 19:38:58 +02:00
Marcus Comstedt
3a8e59319a 8048: Reformat to begin and end each semantic section with NL (unless empty) 2019-07-19 19:38:57 +02:00
Marcus Comstedt
4f6e4bc172 8048: Avoid @ifdef inside a semantic section 2019-07-19 19:38:57 +02:00
Marcus Comstedt
9a1f5e60bf 8048: Avoid use of unquoted # in the display section 2019-07-19 19:38:57 +02:00
Marcus Comstedt
4531aa402f 8048: Avoid use of @define without value 2019-07-19 19:38:56 +02:00
Marcus Comstedt
3dfb8bc974 8048: Avoid use of macro expansion 2019-07-19 19:38:56 +02:00
ghidorahrex
d7877b0353 Updated pcode tests for PIC30 issues. 2019-07-19 13:22:06 -04:00
ghidorahrex
05d9679a3d Added instructions that correctly emulate/model/decompile division for 
the PIC-24 and PIC-30.
 2019-07-19 13:22:05 -04:00
Ryan Kurtz
eba358f1d2 Merge remote-tracking branch 'origin/GT-3018_ghidorahrex_PR-800_mumbel_ARM_vmov_thumb_instruction' 2019-07-19 12:19:49 -04:00
ghidra1
6a6bb63932 Corrected ELF Import issue where FileBytes can not be used in some load 
situations (e.g., PIC-30)
 2019-07-19 10:56:01 -04:00
Philip Pemberton
a8f27f6484 TRAPV/TRAPcc don't use the TRAP7 vector, they use the TRAPV vector 2019-07-18 08:54:54 -04:00
Philip Pemberton
919762c1cc Prefix trap(), make parameter the trap number 
* Add "__m68k_" prefix to `trap()` to indicate that it's a CPU
    intrinsic
  * `__m68k_trap()` now takes the trap number as a parameter, which
    lines up better with established 68k norms (`TRAP #n` is the
    assembly syntax)
 2019-07-18 08:54:28 -04:00
Philip Pemberton
f127c3c0fc M68000: set alignment, full SR decode, TRAPV as address 
* Specify instruction alignment to be 2 bytes
  * Fully decode the status register (add trace and supervisor flags and interrupt priority)
  * Decode TRAPs into the vector addresses to make code easier to follow
 2019-07-18 08:54:09 -04:00
Ryan Kurtz
674d5cee53 Merge remote-tracking branch 'origin/GT-3015_ryanmkurtz_PR-756_Piruzzolo_AAM' 2019-07-18 08:48:30 -04:00
emteere
a842f89e6e GT-2907_emteere Fixed correct setting of CF for lsl.b, lsl.w, asl.b, 
asl.w
 2019-07-18 08:29:29 -04:00
mumbel
7fc76dbca4 [tricore] TRICORE processor module 2019-07-17 18:00:12 -05:00
ghidra1
e565601299 Merge remote-tracking branch 'origin/ghidra1_BitFields' 2019-07-17 18:45:27 -04:00
mumbel
5521906393 vmov instruction was using wrong varaible to allow for THUMB 
and ARM resulting in the wrong register being attached/selected.

The U bit was also flipped `unsigned = (U == '1');`
unsigned now has bit set and signed is unset
 2019-07-17 17:28:53 -05:00