- The EVA instructions have prime=0x1E, this should be 0x1F. These
instructions are used to access user mode virtual address from
kernel mode, so probably not used often.
- General cleanup in the bit pattern. There was mixed used of
decimal and hex values for the same token, converted >9 to hex
- Added OCTEON instructions: lbx, blux, ldx, lhx, lhux, lwx, and lwux
- Implemented the multiple accumulator found in DSP for:
madd, maddu, mfhi, mflo, msub, msubu, mthi, mtlo, mult, and multu
These changes convert '00' to ac in the bit pattern and attach to
the original lo/hi pair and now lo1/hi1, lo2/hi2, and lo3/hi3 pairs.
The value of ac can range from 0 to 3. When ac=0, this refers to
the original HI/LO register pair of the architecture.
- some minor whitespace cleanup
x86 16-bit in IDA Pro >= 7.0 and probably earlier uses the metapc processor type and not any of those listed anymore. I am not sure how many others should also be included but probably all of them. The bit size is the primary selection, not the processor type anymore so although metapc is confirmed, perhaps the following should also be added as they are under 32-bit:
<external_name tool="IDA-PRO" name="80686p"/>
<external_name tool="IDA-PRO" name="k62"/>
<external_name tool="IDA-PRO" name="p2"/>
<external_name tool="IDA-PRO" name="p3"/>
<external_name tool="IDA-PRO" name="athlon"/>
<external_name tool="IDA-PRO" name="p4"/>
Though this is certainly a legacy IDA 5.x and maybe 6.x issue mainly. AFAIK, all the >= 7.0 IDA versions use metapc for all x86. Specific processors were any early feature that was consolidated there.
According to Intel manual, the AAM instruction has a MOD, not an AND. Likely a typo. More, (AF == 1) added instead of AF (but I think it's pretty much the same)
+ bonus typo fix
removing a line that appears to be superfluous. also, fix indentation.
unfortunately, i have *not* tested this, as i noticed this apparent extra line during a visual inspection. i don't have a build environment currently configured.
Note that this doesn't take into account the subtleties of what TEQP
does -- for more information on this, see
https://www.heyrick.co.uk/armwiki/The_Status_register#Legacy_processors_.2826_bit.29
It will, however, stop Ghidra from completely freaking out when it sees
this instruction in old RISC OS 26bit-PC code.
TODO, make this behave (in SLEIGH) like a PSR update (MSR CPSR, ...) but
note that the PSR bit order is different to the 26bit ARM PSR so fudging
will be needed.
