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mumbel d7e51ee515 RISC-V processor 
[riscv] Added context register for extensions

[riscv] missed a define in refactor

[riscv] got 100% on RV32IMC

[riscv] Add throw away script to generate SLEIGH

[riscv]

Fixes from SleighDevTools

- R4-type were using a bad bit pattern that broke the rs3 operand
- mul had a copy/paste typo that ignored the rs2 operand
- bad define guard for compressesed instruction
2019-12-10 14:04:05 -06:00
..
riscv.csr.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.ilp32.slaspec RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.ilp32d.slaspec RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.ilp32f.slaspec RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.instr.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.ldefs RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.lp64.slaspec RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.lp64d.slaspec RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.lp64f.slaspec RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.opinion RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.priv.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.reg.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.rv32a.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.rv32d.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.rv32f.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.rv32i.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.rv32m.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.rv32q.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.rv64a.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.rv64d.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.rv64f.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.rv64i.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.rv64m.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.rv64q.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.rvc.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.table.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv.zi.sinc RISC-V processor 2019-12-10 14:04:05 -06:00
riscv32-fp.cspec RISC-V processor 2019-12-10 14:04:05 -06:00
riscv32-fp.dwarf RISC-V processor 2019-12-10 14:04:05 -06:00
riscv32.cspec RISC-V processor 2019-12-10 14:04:05 -06:00
riscv32.dwarf RISC-V processor 2019-12-10 14:04:05 -06:00
riscv64-fp.cspec RISC-V processor 2019-12-10 14:04:05 -06:00
riscv64-fp.dwarf RISC-V processor 2019-12-10 14:04:05 -06:00
riscv64.cspec RISC-V processor 2019-12-10 14:04:05 -06:00
riscv64.dwarf RISC-V processor 2019-12-10 14:04:05 -06:00
RV32G.pspec RISC-V processor 2019-12-10 14:04:05 -06:00
RV32GC.pspec RISC-V processor 2019-12-10 14:04:05 -06:00
RV32I.pspec RISC-V processor 2019-12-10 14:04:05 -06:00
RV32IC.pspec RISC-V processor 2019-12-10 14:04:05 -06:00
RV32IMC.pspec RISC-V processor 2019-12-10 14:04:05 -06:00
RV64G.pspec RISC-V processor 2019-12-10 14:04:05 -06:00
RV64GC.pspec RISC-V processor 2019-12-10 14:04:05 -06:00
RV64I.pspec RISC-V processor 2019-12-10 14:04:05 -06:00
RV64IC.pspec RISC-V processor 2019-12-10 14:04:05 -06:00