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d7e51ee515
[riscv] Added context register for extensions [riscv] missed a define in refactor [riscv] got 100% on RV32IMC [riscv] Add throw away script to generate SLEIGH [riscv] Fixes from SleighDevTools - R4-type were using a bad bit pattern that broke the rs3 operand - mul had a copy/paste typo that ignored the rs2 operand - bad define guard for compressesed instruction
12 lines
194 B
Text
12 lines
194 B
Text
define endian=little;
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@define XLEN 8
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@define XLEN2 16
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@define FLEN 0
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@define ADDRSIZE "64"
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@define FPSIZE ""
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@include "riscv.reg.sinc"
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@include "riscv.table.sinc"
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@include "riscv.instr.sinc"
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